Time Series Database for Financial Systems
eXtremeDB for HPC offers powerful features for a competitive edge.
eXtremeDB for HPC time series database delivers the most powerful solution for managing market data while maximizing productivity through open, developer-preferred languages, making it the ideal database for financial systems.
What sets eXtremeDB for HPC apart?
Standard features, ideal for financial systems.
eXtremeDB offers a competitive advantage in trading system design, risk, order book and other financial systems via groundbreaking speed as confirmed by audited STAC-M3 benchmarks and other tests.
Easily shard (distribute) data to leverage multiple cores, CPUs and/or servers, while isolating client applications from the complexity with eXtremeDB’s distributed query engine which presents a distributed database as a single contiguous whole and allows for 99.999% uptime high availability.
eXtremeDB offers a full suite of features to maximize reliability including ACID-compliant transactions, a type-safe API, advanced debugging and corruption prevention tools and more.
eXtremeDB ’s fast, native C/C++ API interoperates fully with its SQL API. The native interface is ideal for time-sensitive operations while the SQL API (with its JDBC & ODBC support) permits higher level access and interfacing with external systems.
Built-in feed handlers and support for time series data (e.g. market tick data) stored in a columnar format maximizes the flow of relevant data into CPU cache, for unparalleled execution speed of complex algorithms.
What is pipelining, and how does it reduce latency?
Pipelining is the programming technique in eXtremeDB that accelerates processing by combining the database system’s vector-based statistical functions into assembly lines of processing for market data, with the output of one function becoming input for the next. Calculations are pipelined in order to keep data within CPU cache during its transformation by multiple functions. Without pipelining, interim results from each function would be transferred back and forth between CPU cache and main memory, imposing significant latency due to the relatively lower-bandwidth front side bus (FSB) or quick path interconnect (QPI) between the two.