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Session date: 15 March, 2023
Session: Session 5.6 / Memory
Presenter: President and CEO Steve Graves
Shared Data in asymmetric multiprocessing (AMP) configurations (12382)
Modern system-on-chip (SoC) platforms often have heterogeneous remote processor devices in asymmetric multiprocessing (AMP) configurations. For example, NXP’s i.MX 8 QuadMax includes ARM Cortex-A and Cortex-M CPU cores, often running different operating systems, and hardware to facilitate communication between the Cortex-A and Cortex-M cores. This presentation will explore implementation options to synchronize access to a shared database in asymmetric multiprocessing SoC, and discuss example use cases.
The Embedded World conference in Nuremberg, Germany, is a gold standard for exchanging information about embedded systems. We are honored to have our CEO Steve Graves presenting. Please use the following link to the program schedule and search for session 5.6 Memory.